Samsung Foundry Roadmap: EUV-Based 7LPP for 2018, 3 nm Incomingby Anton Shilov on May 24, 2018 12:00 PM EST
- Posted in
- Samsung Foundry
Samsung Foundry this week updated its fabrication technology roadmap, introducing a number of changes and announcing the first details about its 3 nm manufacturing process that is several years away. The company also reiterated plans to start risk production of chips using its 7LPP process technology and extreme ultraviolet lithography (EUVL) later this year.
Samsung is accelerating its foundry roadmap in a bid to not only keep up with rivals in the foundry industry, but also to enable its SoCs to take advantage of the leading-edge process technologies and offer higher performance or lower power consumption than competing chips. Higher performance and/or lower power allows Samsung to build better mobile devices, such as smartphones, which are the company’s bread and butter. Therefore, being a vertically-integrated company, it makes a great sense for Samsung to stay ahead of any other maker of semiconductors.
|Samsung Foundry Lithography Roadmap, HVM Start
Data announced by company during conference calls, press briefings and in press releases
|*Exact timing not announced
**May be available only to Samsung LSI
7LPP on Track, 5LPP/6LPP Vanish, 5LPE Introduced
Samsung has previously announced plans to start risk production of chips using its 7LPP (7 nm low power plus) process technology and EUVL tools in 2018, and this target remains unchanged. What remains to be seen is when exactly Samsung starts high-volume manufacturing (HVM) of chips using this tech and ASML’s Twinscan NXE equipment. Since the company can offset the high initial costs of chips made on this process by selling complete smartphones (this is where Samsung’s vertical integration starts to pay off), it can kick off HVM of SoCs for the next generation Galaxy S smartphones using its latest fabrication process just months after it starts risk production using 7LPP. What is noteworthy is that Samsung admits that 7LPP IP blocks required for various chips will be ready only by the first half of 2019, so the tech is not ready for prime time just now (but could be ready for Samsung’s own SoCs), pending what smartphone Samsung intends to launch in 1H 2019.
Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to “allow greater area scaling and ultra-low power benefits” when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.
4LPE/4LPP to Retain FinFETs
Samsung's foundry update also laid out the company's plans for more advanced fabrication technologies that they plan to use in the coming years. As it appears, Samsung has decided to prolong the usage of FinFET transistors for leading-edge manufacturing processes. Last year Samsung planned to introduce gate-all-round FETs (GAAFETs) with its 4LPP node in 2020, but the plans have changed since then.
Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.
It is unclear when Samsung plans to start risk production and volume production using its 4LPE and 4LPP process technologies, but if everything goes in accordance with the company’s current process technology cadence, expect Samsung’s 4LPE/4LPP nodes to be used for HVM in the early 2020s.
3 nm to Use GAAFETs
The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung’s own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.
MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung’s fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the EUV in general will have a clear impact on Samsung’s technologies several years down the road.
|Industry Lithography Roadmap, HVM Start
Data announced by companies during conference calls, press briefings and in press releases
|GF||14LPP||12HP||12LP||7nm DUV||7nm EUV
|Intel||14nm+||14nm++||10 nm*||10 nm+*||?||?|
|SMIC||14 nm in development||?||?|
|*Exact timing not announced
**May be available only to Samsung LSI
- Samsung’s 8LPP Process Technology Qualified, Ready for Production
- Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC
- TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains
- Intel Delays Mass Production of 10 nm CPUs to 2019
- TSMC Kicks Off Volume Production of 7nm Chips
- TSMC Starts to Build Fab 18: 5 nm, Volume Production in Early 2020
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shabby - Thursday, May 24, 2018 - linkSlow down samsung, intel is still stuck in double digit nm.
peevee - Thursday, May 24, 2018 - linkWhat about the proper metric, bits (or transistors) per sq mm (in SRAM)? Those "nm" designations have absolutely nothing to do with reality, pure marketing. And it would be great if everybody would slow down their marketing, because for a long time it is just fraud.
Intel's "10 nm" process have been a total failure of course, even if they start mass production on it today and even if it is going to be faster and more energy efficient than "14+++", in terms of time and cost it took.
It would be fantastic if Anandtech could have an investigation into what has happened, conducting some interviews with anonymous sources currently or formerly with Intel. Have they lost real talent? To whom, Samsung? Did they elevate wrong, incompetent people into management? Have they been affected by political considerations, like pushing "diversity" instead of ultimate competence?
p1esk - Thursday, May 24, 2018 - linkI like the idea of such interviews. That would be real journalism in action.
MrSpadge - Thursday, May 24, 2018 - linkFrom what I read it seems like their 10 nm process was just too ambitous. They get the best density among competing processes, if they're successful, but require 5-6 lithography steps for the critical layers. TSMC and SLI get away with quadruple patterning, which yields a lower density of transistors but increases yield. Better have one bird in the hand than 2 on the roof.
jwcalla - Thursday, May 24, 2018 - linkinb4 somebody mentions that Samsung 3nm is still larger than Intel 32nm... since we hear that story on every one of these articles.
A5 - Thursday, May 24, 2018 - linkColor me skeptical that SLI is going to launch a notably improved process every 6 months for the next 3 years. Even TSMC is only talking about 1 a year.
And I'll be very surprised if Intel is still on 10nm+ for their front-line designs in 2021.
name99 - Friday, May 25, 2018 - linkWhat counts as “significantly” improved? Rather than sneering at SS, LEARN from them.
The reason they (and TSMC) are not floundering like INTC is that they don’t go in for your “significant” improvements; they go in for small tweaks every few months. Then when something fails, it’s not a catastrophe to figure out the problem and correct.
Compare with INTC trying to boost density by 2.7x in one leap by boiling the ocean — and then discovering that they’re going to need a bigger blowtorch than they have available...
rocky12345 - Thursday, May 24, 2018 - linkI am gonna guess that all of these companies that rushed down the nano meter scale so fast the last few years are wishing they would have slowed down years ago and just worked out the problem og the bigger nm nodes back then so they would not be in a pickle like they will be in the near future when they have no where left to go except invent something totally new to work with.
FullmetalTitan - Friday, May 25, 2018 - linkNo one "rushed down the scale" in any way. Each of those nodes generally has a major process change to either transistor design or interconnect scheme, justifying the 'node' shrink based on performance gains. LSI definitely likes to market a minor change as bigger than such, more than the others probably. However, the current issues with these technologies didn't EXIST at higher nodes (except Intel's problems with 10nm, they scaled geometry too aggressively without changing fundamental design, hence hexa-patterning), so they aren't unsolved problems everyone just lives with while forging ahead.
attila123 - Sunday, January 19, 2020 - linkWell in 2019 they went to 3nm. Which most people thought was impossible.