Estimating Intel-Micron 32-layer 3D NAND Die Size
by Kristian Vättö on March 27, 2015 5:55 AM EST
Yesterday Intel and Micron shared some new details of their 3D NAND technology and during the presentation they also showed a production wafer. I missed the wafer during the live broadcast (hence I couldn't include this in the initial write up), but fortunately Intel-Micron have now posted the recorded webinar, which I used to get a pretty good shot of the wafer. The quality isn't perfect, but it's good enough that I was able to make a fairly accurate estimation of the die size.
Disclaimer: The data and analysis presented in this article is based on estimations that are provided "as is" with no guarantee of full accuracy.
I calculated 19 dies vertically and 25 horizontally, which would yield a die size of 189.5mm. That's a bit too high since it doesn't take the partial dies on the edges of the wafer into account, so when taking that and the die cuttings (i.e. the space between dies) into account, my estimation of the die size would be 175mm. I think in reality it might be closer to 170mm, but I'll rather be conservative than present too optimistic numbers.
My die size estimation goes pretty well hand-in-hand with Intel-Micron's planar NAND dies. The two have never really focused on building small dies for mobile applications (e.g. microSD cards), which is why the die sizes are higher compared to the others with mobile focus. I was told Intel-Micron might build a smaller two-plane 3D NAND for mobile use if they see demand for it, but as I mentioned in yesterday's news post the initial die will be a 4-plane design that is aimed for SSDs.
Now that we have the die size we can also estimate the most important metric i.e. the bit density. Intel-Micron's 32-layer 3D NAND design is by far more efficient than Samsung's, which is mostly explained by the much higher die capacity. The memory array efficiency (i.e. the portion of the die that's dedicated to memory cells) tends to scale with die capacity because the peripheral circuitry doesn't need too many modifications and thus the die area taken by the circuitry doesn't really increase with capacity.
I estimated Intel-Micron's 32-layer 3D NAND to have array efficiency of approximately 85%, which is very good and considerably higher than Samsung's 32-layer design (66% for the 86Gbit MLC part and 72% for the 128Gbit TLC part). Samsung did some peripheral circuitry optimizations for the 32-layer TLC part that explain the higher array efficiency versus the MLC part. When assuming similar array efficiencies for Intel-Micron and Samsung TLC dies, the bit densities are actually equivalent, suggesting that from a lithography and cell size perspective the two designs should be quite similar.
I now understand why Intel-Micron claim that their 3D NAND technology comes with disruptive cost because it really is the most efficient 3D NAND technology we have seen so far. It has twice the bit density compared to Micron's latest 16nm 128Gbit die, which should be enough to mitigate the higher production cost per wafer and make 3D NAND a natural successor to Intel-Micron's planar NAND. It will be interesting to see how Samsung's third generation V-NAND stacks up against Intel-Micron's 32-layer 3D NAND, but it's clear that Samsung must be able to increase the die capacity to remain competitive as it's more than just a game of layers.
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stephenbrooks - Friday, March 27, 2015 - link
I'm curious where this is going to go once they require 100s of layers -- a huge pipeline of lithography machines with one wafer taking months to build up all the layers?ats - Friday, March 27, 2015 - link
It already takes months for normal production wafers with a planar design. The primary advantage of multi-layer is a significant increase in tolerance around litho-etch. This can result in an increased throughput per lith-etch stage. Also for <20nm, there are multiple layers that have to have multiple litho-etch steps. Multi-layer basically doesn't need multiple patterning. What it all means is that while multi-layer has more total die layers, it can have less overall steps to get those layers in some cases and those steps can go faster. Multi-layer also generally will result in larger charge capture structures leading to longer endurance as well than the equivalent density on a planar design.stephenbrooks - Sunday, March 29, 2015 - link
Interesting, so they are already limited by the speed of the steps? If a 1% increase in litho scale is more than 2% faster they can achieve more bits per wafer at the larger scale.hojnikb - Friday, March 27, 2015 - link
Any reason why MLC V-nand die bigger than TLC ?I mean, they are the same layer count and same node AND MLC die is smaller in capacity.
If everything, these two should be the same, since if cutting 128Gbit TLC to MLC yields around 86Gbit.
MrSpadge - Friday, March 27, 2015 - link
Optimization of the peripheral circuitry according to the article.dealcorn - Friday, March 27, 2015 - link
is the die size small enough to permit on package fabrication with a 14nm Atom class CPU? A smartphone SoC with an economical, reasonably efficient, on package SSD might have appeal if it reduces BoM costs.extide - Friday, March 27, 2015 - link
NAND processes are totally different to logic processes, not really comparable.dealcorn - Friday, March 27, 2015 - link
On package means not on the same die. Different logic processes are irrelevant.alacard - Friday, March 27, 2015 - link
I'd still go with Samsung as the charge trap flash technology is pretty incredible, and i'm more interested in cell reliability than density. When it comes to storing my data I always choose quality over quantity.If the tech reviewers give the different cell technologies a fair shake when reviewing drives, i think most users will agree and spring for the more expensive more durable flash which will bring costs down and force Intel-Micron-Toshiba to improve their technology.
If they don't... let the race to the bottom commence.
frenchy_2001 - Friday, March 27, 2015 - link
1) Reliability is the sum of many factors. Die type (planar, 3D, charge trap or floating gate) is only one2) Tech Report just finished a SSD reliability experiment. It took them almost a year to kill planar MLC 256GB SSDs by writing over 1PB of data. Unless you are dealing with uncompressed 4k video on a daily basis, reliability for consummer from NAND exhaustion is a non-issue.
3) Testing for this is a *VERY* long process. Reviewers like Anandtech test what the smart parameters report, but those are usually programmed to the guaranteed reliability (in this case, would be 3000). Real, tested reliability would take a reviewer writing till the SSD dies, like the techreport experiment. With 256Gb dies with 10k cycles expected, it will take a LONG while...
4) Market has proven that consummers go for convenience and costs first. Few will research the underlying tech and the differences.
5) technology will continue improving none the less (NAND is a competitive market and other techs like RRAM are coming up)