Analyzing the iPhone 5 Geekbench Results

While working on our Haswell piece, I've been religiously checking the Geekbench and GLBenchmark results browsers to see if anyone ran either benchmark and decided to tap upload. This usually happens before every major smartphone launch, but in the case of the iPhone 5 the details these applications can give us are even more important.

Yesterday we confirmed that Apple is using its own custom designed ARM based CPU cores in its A6 SoC. Apple opted not to design in a vanilla ARM Cortex A9 likely to avoid relying on pure voltage/frequency scaling to improve performance, and chose not to integrate a Cortex A15 likely because of power consumption concerns as well.

There's absolutely no chance of Apple sending us a nice block diagram of the A6 CPU cores, so we have to work with what clues we can get elsewhere. Geekbench is particularly useful because it reports clock speed. Why does clock speed matter? Because, if reported accurately, it can tell us a lot about how the A6's CPU design has improved from an IPC standpoint. Remember that clock speed doesn't matter, but rather the combination of clock frequency and instructions executed per clock that define single threaded performance.

A short while ago, Geekbench results for a device identifying itself as an iPhone5,2 appeared. Brian believes this is likely the A1429 Verizon device (A1428 being iPhone 5,1) - perhaps one presampled to a reviewer looking to test their luck.

MacRumors appears to be first on the scene, having been tipped by an employee at PrimateLabs (the creators of Geekbench). I need to preface the rest of this post with a giant caution sign: I have no inside knowledge of whether or not these results are legitimate. They seem believable, but anything can happen. The rest of this post is simply my initial thoughts on what these mean, should the results be accurate. Update: The first iPhone 5 reviews are out and this Geekbench data looks accurate.

Cache sizes haven't changed, which either tells us Apple isn't feeling as generous with die size as perhaps it once was or that working sets in iOS are still small enough to fit inside of a 1MB L2. I suspect it's mostly the latter, although all microprocessor design is a constantly evaluated series of tradeoffs (often made through giant, awesomely protected spreadsheets). 

The first real change is clock speed. Apple clocked its A4 and A5 CPU core(s) at 800MHz, although these Geekbench results point to a 25% increase in frequency at 1GHz. Some of the headroom is likely enabled by the move to 32nm, although it's very possible that Apple also went with a slightly deeper pipeline to gain frequency headroom. The latter makes sense. We've seen conservative/manageable increases in pipeline depth to hit frequency targets and improve performance before. 

The fairly low clock speed also points to an increase in IPC (instructions executed per clock) over the Cortex A9 design. As I mentioned in our A6 analysis post, simple voltage/frequency scaling is a very power inefficient way to scale performance. A combination of IPC and frequency increases are necessary. If these results are accurate and the CPU cores are only running at 1GHz, it does lend credibility to the idea of a tangibly wider design.

It's also unclear if Apple is doing any sort of dynamic thermal allocation here, ala Intel's Turbo Boost. You can't get more power constrained than in a smartphone, and power gating is already common within ARM based SoCs, so that 1GHz value could be under load for both cores. A single core could run at higher frequencies for short bursts. 

The next thing that stood out to me was the memory data:

It's well known that ARM's Cortex A9 doesn't have the world's best interface outside of the compute core and its memory performance suffered as a result. If this data is accurate, it points to significantly overhauled cache and memory interfaces. Perhaps an additional load port, deeper buffers, etc...

Also pay close attention to peak bandwidth utilization. The 4S had 6.4GB/s of theoretical bandwidth out to main memory, the 5 raises that to 8.5GB/s. In the Stdlib write test the 4S couldn't even hit 50% of that peak bandwidth. The iPhone 5 on the other hand manages to hit over 70% of its peak memory bandwidth. I will say that if these numbers are indeed faked, whoever faked them was smart enough not to violate reality when coming up with these memory bandwidth numbers (e.g. no 95% efficiency numbers show up). It's also clear that these results aren't a simply doubling across the board over the 4S, lending some credibility to them.

Some of the largest performance improvements promised by the Geekbench data appear here in the memory results. It's whatever work Apple did here that helped enable the gains in the integer and floating point results below:

On average we see around 2.2x scaling from the 4S to the 5 in Geekbench's integer tests. There's no major improvement in multicore scaling, confirming what Geekbench tells us that we're looking at a two core/two thread machine. 

The gains here are huge and are likely directly embodied in the performance claims that Apple made at the iPhone 5 launch event. Many smartphone workloads (under Android, iOS and Windows Phone despite what Microsoft may tell you) are still very CPU bound. Big increases in integer performance will be apparent in application level improvements.

Don't be surprised to see greater than 2x scaling here even though Apple only promised 2x at the event. Remember that what you're looking at is raw compute tests without many of the constraints that apply to application level benchmarks. While Apple has used benchmarks in the past to showcase performance, all of its performance claims at launch were application level tests. Those types of tests are more constrained and will show less scaling. That being said, I am surprised to see application level tests that were so close to the 2.2x average scaling we see here. Apple could have moved to faster NAND/storage controller here as well, which could help most if not all of these situations.

The floating point benchmarks show "milder" scaling in the first few tests (sub-2x) but big scaling in the latter ones. My guess here is we're seeing some of the impacts of increased memory bandwidth at the end there. If you look at our iPhone 5 hands-on video you'll see Brian talking about how super fast the new flyover mode in iOS 6 Maps is on the 5 compared to the 4S. That's likely due in no small part to the improved memory interface.

Although Geekbench is cross platform, I wouldn't recommend using this data to do anything other than compare iOS devices. I've looked at using Geekbench to compare iOS to Android in the past and I've sometimes seen odd results.

I'm sure we'll learn a lot more about the A6 SoC over the coming days/weeks.