Foundries started limited usage of extreme ultraviolet (EUV) lithography for high-volume manufacturing (HVM) of chips in 2019. At the time, ASML's Twinscan NXE scanners were good enough for production, but the full EUV ecosystem was not quite there. One of the things that impacted EUV was the lack of protective pellicles for photomasks, which limited usage of EUV tools and affected yields. Fortunately, the situation with pellicles has finally improved thanks to the recent introduction of production-ready EUV pellicles, and matters promise to get even better in the coming years.

Protecting Precious Reticles

ASML has made a great progress with its Twinscan NXE EUV lithography tools in the recent years, improving performance of light source, availability time, and productivity. Its industry peers have also done a lot to make high-volume manufacturing (HVM) using EUV equipment possible. Still, the EUV ecosystem needs to develop further. One of the most notorious challenges the semiconductor supply chain faced with EUV is development of pellicles that were not available two years ago, which is why TSMC and Samsung Foundry had to invent ways how to use their EUV scanners without protective films.

For Reference: A 16nm TSMC Pellicle With Reticle

Pellicles protect 6×6-inch photomasks (reticles) during the chip production flow by sealing them away from particles that could land on their surface, which would otherwise damage them or introduce defects to wafers in production. Each reticle for an EUV tool costs $300,000, so chipmakers are eager to protect them against damage by particles or even the EUV radiation itself as this lowers their costs. Meanwhile, reducing risks associated with yields is perhaps even more important.

The need for pellicles, in turn, varies depending on the manufacturer and the types of photomasks employed. Intel, which is known for its big CPU dies, tends to use single-die reticles, which means that just one mask defect introduced by a particle automatically kills the whole die. Meanwhile, if a 25-die photomask is used, a particle adder will 'only' result in 4% lower yield (one dead die), which is why it's been possible to get away without pellicles for smaller chips and multi-die photomasks.

ASML Leading the Pack. For Now

The industry started to develop protective films for EUV tools relatively late after it transpired that nobody can guarantee that an ultra-complex EUV scanner is 100% free of harmful particles, which is why they were not ready in 2019.

Pellicles for photomasks to be used with deep ultraviolet (DUV) lithography equipment are common and cheap. By contrast, since photomasks for EUV are different from photomasks for DUV (EUV masks are essentially 250 to 350-nm thick stacks featuring 40 to 50 alternating layers of silicon and molybdenum on a substrate), pellicles for such reticles are also quite different. In particular, the very short wavelength of EUV means that pellicles for it have a number of requirements that make them uneasy to produce and expensive. EUV pellicles have to be extremely thin, should not affect reflection characteristics of reticles, should feature a high transmission rate (the higher the rate, the higher is productivity of a scanner), should sustain high EUV power levels, and withstand extreme temperatures (from 600ºC to 1,000ºC in the future).

ASML's EUV Pellicle (Image Credit: Semiconductor Engineering)

"Most materials absorb very strongly at the more energetic 13.5nm EUV wavelength and, even when the most EUV-transparent materials are selected, the membranes must be extremely thin to approach 90% transmittance," said Emily Gallagher, a principal member of technical staff at Imec. "Such thin membranes are not usually capable of maintaining sufficient strength to be free-standing at the required dimensions. Additionally, the EUV scanner environment is not compatible with many materials and will subject the pellicle to pump-vent cycles."

To date, a number of EUV pellicle options have emerged, according to SemiEngineering:

  • ASML introduced its first EUV pellicles in 2019 and licensed the technology to Mitsui Chemicals, which intends to start their volume sales in Q2 2021. Since then, ASML has improved its pellicles.
  • Imec has disclosed test results of its pellicles based on carbon nanotubes.
  • Graphene Square, Freudenberg Sealing Technologies (FST), and some universities are developing their own pellicles.

So far, only ASML has managed to create commercially viable pellicles for EUV tools that are actually available. ASML's pellicles are based on polysilicon that is 50 nm thick. Back in 2016, they demonstrated a 78% transmissions rate on a simulated 175W source. Currently ASML can sell a pellicle with an 88% transmission rate. And shortly, Mitsui will start supplying such pellicles in volume.

ASML's latest prototypes made of metal silicide demonstrate a 90.6% transmission rate with 0.2% non-uniformities and less than 0.005% reflectivity on a 400W source.

"This upgrade supports our roadmap, which eventually will take source power up to 400 Watts," said Raymond Maas, ASML’s product manager for pellicles, in an interview with Bits& "The pellicle heats up to 600ºC at that power level, which the polysilicon couldn’t withstand."

By contrast, Imec's prototype pellicles have a transmission rate of 97.7%. In fact, in the long term, when more advanced light sources are available, more sophisticated pellicles will be needed and this is where Imec's carbon nanotubes-based pellicles will come into play.

"Few materials have the potential of high EUV transmission beyond 90% and even fewer materials are at the same time compatible with EUV powers beyond 600W. In addition, the pellicle needs to be strong to be suspended over a large area of the mask (~110mm x 140mm)," said Joost Bekaert, a researcher from Imec.

Unfortunately, it is unclear when Imec's carbon nanotube-based pellicles will be ready for primetime.


TSMC and Samsung Foundry have invented ways to use EUV lithography tools without pellicles on multi-die photomasks for smaller chips, but such methods are risky as any particle adder can become a yield killing defect. Furthermore, such methods are risky for bigger chips and single-die photomasks, so pellicles are critical for enabling large dies to be made with EUV tools. That said, regardless of the photomask size, pellicles are needed to improve EUV yields and reduce risks across the board.

Overall then, the use of and improvements in EUV pellicles will be a gradual process. The initial pellicles developed and made by ASML and soon to be made by Mitsui are good enough for some of today's needs, but there is room for improvement with their transmission levels, as evidenced by the next-generation prototypes developed by ASML and Imec. Better pellicles will be needed to account for future scanners as well, since those machines will have more powerful sources. Nonetheless, since such pellicles have a number of indisputable advantages, they are going to be used by chipmakers as they can help to improve yields even at the cost of some productivity.

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  • Spunjji - Friday, April 2, 2021 - link

    Yeah, I was confused by that take too. Intel tried really hard to hold back on EUV and they've very clearly paid the price, so something tells me it's not quite as simple as "larger mask".
  • TristanSDX - Friday, April 2, 2021 - link

    I talk about law of physics here. Creating tools with large masks philosophy, probably require long and large investments, and nobody want to risk money. Beside of this there is 'common sense', kind of belief that only one way will work best, until someone prove otherwise.
  • Duncan Macdonald - Friday, April 2, 2021 - link

    If Intel is using single CPU reticles (at least for its larger CPU dies) does that not imply a slower throughput in the masking step ?
    Is this single CPU reticle due to some other constraint in Intel's tool chain making it difficult for Intel to produce (or use) a larger reticle ?

    A separate note - Intel says that it is going to invest $20 billion in 2 new fabs - TSMC is going to invest $100 billion over the next 3 years.
  • basroil - Friday, April 2, 2021 - link

    "If Intel is using single CPU reticles (at least for its larger CPU dies) does that not imply a slower throughput in the masking step ?"

    More likely it just means the bottleneck is elsewhere, likely energy density, and it's just that Intel and other makers have different approaches to the same problem. If you need X joules/mm^2 to properly expose a mask, and your lamp is y watts, you can do one of two things:
    1) Make a smaller mask, focus those Y watts into Z mm^2 for T=X*Z/Y seconds
    2) Make a larger mask, focus those Y watts into 4*Z mm^2 for T=4*X*Z/Y seconds

    In the end, your patterns/second is unchanged since your actual bottleneck is the source power. Of course there are other factors like:
    * Single masks are easier to position because your stacking tolerance is actually smaller
    * Multimasks are faster to position since you only need one move every 4 patterns
    * Single masks improve yields for multiple layers due to positioning
    * Multimasks improve yields because one bad pattern only removes that many chips from yield
    * Single mask reticles are cheaper to make since substrate is smaller and pattern larger (usually)
    * Multimasks have longer usability period since multiple flaws are less likely to be on the same pattern
    (and so on)

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