With transistor shrinks slowing and demand for HPC gear growing, as of late there has been an increased interest in chip solutions larger than the reticle size of a lithography machine – that is, chips bigger than the maximum size that a single chip can be produced. We've already seen efforts such as Cerebras' truly massive 1.2 trillion transistor wafer scale engine, and they aren't alone. As it turns out, TSMC and Broadcom have also been playing with the idea of oversized chips, and this week they've announced their plans to develop a supersized interposer to be used in Chip-on-Wafer-on-Substrate (CoWoS) packaging.

Overall, the proposed 1,700 mm² interposer is twice the size of TSMC's 858 mm² reticle limit. Of course, TSMC can't actually produce a single interposer this large all in one shot – that's what the reticle limit is all about – so instead the company is essentially stitching together multiple interposers, building them next to each other on a single wafer and then connecting them. The net result is that an oversized interposer can be made to function without violating reticle limits.

The new CoWoS platform will initially be used for a new processor from Broadcom for the HPC market, and will be made using TSMC's EUV-based 5 nm (N5) process technology. This system-in-package product features ‘multiple’ SoC dies as well as six HBM2 stacks with a total capacity of 96 GB. According to Broadcom's press release, the chip will have a total bandwidth of up to 2.7 TB/s, which is in line with what Samsung’s latest HBM2E chips can offer.

By doubling the size of SiPs using its mask stitching technology, TSMC and its partners can throw in a significantly higher number of transistors at compute-intensive workloads. This is particularly important for HPC and AI applications that are developing very fast these days. It is noteworthy that TSMC will continue refining its CoWoS technology, so expect SIPs larger than 1,700 mm2 going forward.

Greg Dix, vice president of engineering for the ASIC products division at Broadcom, said the following:

"Broadcom is happy to have collaborated with TSMC on advancing the CoWoS platform to address a host of design challenges at 7nm and beyond. Together, we are driving innovation with unprecedented compute, I/O and memory integration and paving the way for new and emerging applications including AI, Machine Learning, and 5G Networking."

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Source: TSMC

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  • Threska - Thursday, March 5, 2020 - link

    Maybe even better VR headsets. They certainly are lots of power in a small package.
  • Holliday75 - Thursday, March 5, 2020 - link

    Silicon that large is going to cost a fortune. I don't see that being an application.
  • Diogene7 - Thursday, March 5, 2020 - link

    What would be the 1. approximative power consumption of such chip and 2. approximative manufacturing cost of such chip ?

    I am wondering when we could hope cost and power consumption to come down enough to have such technologies in a smartphone ?

    I wish there would exist Non Volatile Memory (NVM) HBM memory like a HBM based on SOT-MRAM or Nanotube RAM (NRAM), and then make a smartphone with at least 128GB / 256GB of SOT-MRAM HBM : it would make for an extremely fast and responsive smartphone :).

    But realistically, it is unlikely to happen before ~2030 I think, until technology mature enough and cost come down...
  • Valantar - Thursday, March 5, 2020 - link

    1700mm2 is likely not much smaller than the average smartphone motherboard, let alone SoC, so...

    This is for HPC and similar applications, at best AICs for workstations. Definitely not applicable for mobile.if you're just taking about using interposers and stacking chips, that's been around for a while. It's not used in mobile due to cost and heat density I would guess. No reason to stick HBM to your SoC if it can't use the bandwidth for anything.
  • Holliday75 - Thursday, March 5, 2020 - link

    Pulling a number out of my rear.......1nm or smaller will need to be the process used to squeeze that much into a chip small enough and efficient enough to be in a cell phone. This chip is going to be HUGE and suck down plenty of juice. Need the process technology to be multiple factors smaller to squeeze it in.
  • Arsenica - Thursday, March 5, 2020 - link

    "and will be made using TSMC's EUV-based 5 nm (N5) process technology"

    This is obviously an incorrect statement as an interposer doesn't really need N5 technology (i.e. a metal pitch of around 35nm).

    TSMC only claims that it is "ready to support TSMC’s next-generation five-nanometer (N5) process technology" with this interposer and that only means it will be validated with N5 chips, but the interposer doesn't need any technology more advanced that what TSMC is using for the upper BEOL layers (that should be in the 100 nm to microns range).
  • name99 - Thursday, March 5, 2020 - link

    "With transistor shrinks slowing"
    Citation needed...

    Just because Intel can't find its ass with both hands and a flashlight doesn't mean everyone else is equally clueless.

  • anivarti - Thursday, March 4, 2021 - link

    Is it some new AI accelerator from BCOM? Why they don't talk anything about FP Tops

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