On the back of Intel’s Technology and Manufacturing Day in March, the company presented another iteration of the information at an equivalent event in Beijing this week. Most of the content was fairly similar to the previous TMD, with a few further insights into how some of the technology is progressing. High up on that list would be how Intel is coming along with its own 10nm process, as well as several plans regarding the 10nm product portfolio.

The headline here was ‘we have a wafer’, as shown in the image above. Intel disclosed that this wafer was from a production run of a 10nm test chip containing ARM Cortex A75 cores, implemented with ‘industry standard design flows’, and was built to target a performance level in excess of 3 GHz. Both TSMC and Samsung are shipping their versions of their ‘10nm’ processes, however Intel reiterated the claim that their technology uses tighter transistors and metal pitches for almost double the density of other competing 10nm technologies. While chips such as the Huawei Kirin 970 from TSMC’s 10nm are in the region of 55 million transistors per mm2, Intel is quoting over 100 million per mm2 with their 10nm (and using a new transistor counting methodology).

Intel quoted a 25% better performance and 45% lower power than 14nm, though failed to declare if that was 14nm, 14+, or 14++. Intel also stated that the optimized version of 10nm, 10++, will boost performance 15% or reduce power by 30% from 10nm. Intel’s Custom Foundry business, which will start on 10nm, is offering customers two design platforms on the new technology: 10GP (general purpose) and 10HPM (high performance mobile), with validated IP portfolios to include ARM libraries and POP kits and turnkey services. Intel has yet to announce a major partner in its custom foundry business, and other media outlets are reporting that some major partners that had signed up are now looking elsewhere.

Earlier this year Intel stated that its own first 10nm products would be aiming at the data center first (it has since been clarified that Intel was discussing 10nm++). At the time it was a little confusing, given Intel’s delayed cadence with typical data center products. However, since Intel acquired Altera, it seems appropriate that FPGAs would be the perfect fit here. Large-scale FPGAs, due to their regular repeating units, can take advantage of the smaller manufacturing process and still return reasonable yields by disabling individual gate arrays with defects and appropriate binning. Intel’s next generation of FPGAs will use 10nm, and they will go by the codename “Falcon Mesa”.

Falcon Mesa will encompass multiple technologies, most noticeably Intel’s second generation of their Embedded Multi-Die Interconnect Bridge (EMIB) packaging. This technology embeds the package with additional silicon substrates, providing a connection between separate active silicon parts much faster than standard packaging methods and much cheaper than using full-blown interposers. The result is a monolithic FPGA in the package, surrounded by memory or IP blocks, perhaps created at a different process node, but all using high-bandwidth EMIB for communication. On a similar theme, Falcon Mesa will also include support for next-generation HBM.

Possibilities with EMIB

Among the IP blocks that can be embedded via EMIB with the new FPGAs, Intel lists both 112 Gbps serial transceiver links as well as PCIe 4.0 x16 connectivity, with support for data rates up to 16 GT/s per lane for future data center connectivity. This was discussed at the recent Hot Chips conference, in a talk I’d like to get some time to expand in a written piece.

No additional information was released regarding 10nm products for consumer devices.

Related Reading

Additional: 1:00pm September 19th

After doing some digging, we have come across several shots of the wafer up close.

From http://news.mydrivers.com/

This is from the presentational display. Detail is very hard to make out at the highest resolution we can find this image.

Additional: 1:20pm September 19th

Intel has also now put the presentation up on the website, which gives us this close-up:

Surprisingly, this wafer looks completely bare. Either this is simply a 300mm wafer before production, or Intel have covered the wafer on purpose with a reflective material to stop prying eyes. It's a very odd series of events, as Intel did have other wafers at the event, including 10nm using ARM, and examples of the new 22FFL process.

From http://news.mydrivers.com/

From http://news.mydrivers.com/

Both of these wafers seem to have a repeating pattern we would typically see on a manufactured wafer. So either Intel does not want anyone to look at 10nm Cannon Lake just yet, or they were just holding up an unused disc of silicon.

Additional: 3:00pm September 20th

Intel got back to us with a more detailed Cannon Lake image, clearly showing the separate dies:

Manual counting puts the wafer at around 36 dies across and 35 dies down, which leads to a die size of around 8.2 mm by 8.6 mm, or ~70.5 mm2 per die. At that size, it would suggest we are likely looking at a base dual-core die with graphics: Intel's first 14nm chips in a 2+2 configuration, Broadwell-U, were 82 mm2, so it is likely that we are seeing a 2+2 configuration as well. At that size, we're looking at around 850 dies per wafer.

Source: Intel

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  • willis936 - Tuesday, September 19, 2017 - link

    I don't see why it wouldn't scale up. Much like simulink (and Not like labview) there should be a code generation option. Furthermore orcad capture style software scales up to systems as large as FPGAs. Abstraction works. There are more and easier ways to become disorganized compared to traditional code so I can see why people would shy away from it. I do however think it'd be incredibly powerful.
  • flgt - Tuesday, September 19, 2017 - link

    Text based design will always be more efficient and maintainable in the hands of a skilled engineer. You actually can enter the design schematically in most of the FPGA vendor tools, but no serious design teams do it on complex designs. Plus there is other peripheral information that must be brought into the design such as timing constraints that make batching up text files a simpler approach. We're not even gonna get into simulation/verification here which is where a lot of the heavy lifting is.

    Tools like Simulink code generation are OK for algorithms but quickly fall apart for peripheral functions you need for real designs. You basically need to be an HDL expert to make sure it's doing what you really intended. It's not the holy grail Mathworks marketing will tell you it is.
  • flgt - Tuesday, September 19, 2017 - link

    Same can be said for software, which is why I wish LabVIEW would go away. It's hard to enforce coding standards on a picture, and you quickly find the developers take forever to do simple things that could be done is a few lines of text source code.
  • willis936 - Wednesday, September 20, 2017 - link

    What would make it a game changer is that it would make FPGA development more accessible. If I wanted to buy a 100 dollar FPGA, plunk down some I/O and logic blocks, tweak a few things, and synthesize, I’d be happy. The number of people capable of working with FPGAs would increase tenfold and maybe clever inventions would from them would become more common.
  • BoyBawang - Tuesday, September 26, 2017 - link

    I am thinking of an Operating system that is FPGA. Bootup speed must be very fast.
  • Notmyusualid - Tuesday, September 19, 2017 - link

    @ SharpEars

    Yep - that is what certainly has my attention too.
  • StevoLincolnite - Tuesday, September 19, 2017 - link

    Still using a 32nm SB-E CPU. So hopefully 10nm Intel CPU's offers the right price/performance to tempt me to upgrade.
  • siberian3 - Tuesday, September 19, 2017 - link

    couple of years would be disaster for intel
  • MajGenRelativity - Tuesday, September 19, 2017 - link

    True, so let's hope they move things along.
  • MrSpadge - Tuesday, September 19, 2017 - link

    That wafer looks more like 300 mm rather than 10 nm ;)

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